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ISL54047
Data Sheet May 31, 2007 FN6503.0
Ultra Low ON-Resistance, High OffIsolation, Single Supply, Diff SPST Analog Switch
The Intersil ISL54047 device is a low ON-resistance, low voltage, high off-isolation, bidirectional, differential singlepole/single-throw (SPST) analog switch. It was designed to operate from a single +1.65V to +4.5V supply. Targeted applications include battery powered equipment that benefit from low RON (0.44) and fast switching speeds (tON = 40ns, tOFF = 35ns). The digital logic input is 1.8V logic-compatible when using a single +3V supply. The ISL54047 has been designed with a T-switch architecture. This approach results in maximum off-isolation while retaining a low impedance signal path when switches are ON. The device can be used as a low impedance bypass element for noisy amplifier circuits. The ISL54047 has two normally open (NO) SPST switches that are controlled by a single logic control pin.
TABLE 1. FEATURES AT A GLANCE ISL54047 Number of Switches SW 4.3V RON 4.3V tON/tOFF 3V RON 3V tON/tOFF 1.8V RON 1.8V tON/tOFF Package 2 SPST 0.44 40ns/35ns 0.51 50ns/40ns 0.98 70ns/65ns 10 Ld 1.8 x 1.4 x 0.5mm TQFN
Features
* T-Switch Architecture * OFF-Isolation at 100kHz - Into 50 Load . . . . . . . . . . . . . . . . . . . . . . . . . . . 102dB - Into 8 Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118dB * ON Resistance (RON) - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.44 - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.51 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.98 * RON Matching Between Channels . . . . . . . . . . . . . . . . 0.04 * RON Flatness Across Signal Range . . . . . . . . . . . . . . . 0.07 * Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V * Low Power Consumption (PD). . . . . . . . . . . . . . . <0.45W * Fast Switching Action (V+ = +4.3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ns * ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV * 1.8V Logic Compatible (+3V supply) * Low ICC Current when VinH is not at the V+ Raill * Available in 10 lead 1.8 x 1.4 x 0.5mm TQFN * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Battery powered, Handheld, and Portable Equipment - Cellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment * Audio and Video Switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54047 Pinout
(Note 1) ISL54047 (TQFN) TOP VIEW
COM2 GND
Truth Table
LOGIC 0 1
5
COM1
NO1, NO2 OFF ON
7
N.C.
6
8
NOTE:
Logic "0" 0.5V. Logic "1" 1.4V with a 3V supply.
N.C.
9
4
IN
Pin Descriptions
PIN FUNCTION System Power Supply Input (+1.65V to +4.5V) Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin No Connect V+ GND IN COMx NOx N.C.
NO2
10 1
V+
3 2
NO1
N.C.
NOTE: 1. Switches Shown for Logic "0" Input.
Ordering Information
PART NUMBER (Note) ISL54047IRUZ-T D PART MARKING TEMP. RANGE (C) -40 to +85 PACKAGE (Pb-Free) 10 Ld 1.8 x 1.4 x 0.5mm TQFN Tape and Reel PKG. DWG. # L10.1.8x1.4A
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
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Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V Input Voltages NO, IN (Note 2) . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Continuous Current NO, COM . . . . . . . . . . . . . . . . . . . . . . . 300mA Peak Current NO, COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA ESD Rating: HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kV
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Ld TQFN Package (Note 3) . . . . . 143 61 Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. Extended operation above the recommended operating conditions could result in decreased reliability. The Absolute Maximum Ratings are stress only ratings and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on NOx, IN, or COMx pins exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 3.9V, ICOM = 100mA, VNO = 0V to V+, (See Figure 4) V+ = 3.9V, ICOM = 100mA, VNO = Voltage at max RON, (Note 7) V+ = 3.9V, ICOM = 100mA, VNO = 0V to V+, (Note 6) 25 Full 25 Full 25 Full
0 -100 -195 -100 -195
0.45 0.55 0.04 0.04 0.07 0.08 -
V+ 100 195 100 195
V nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO OFF Leakage Current, INO(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 4.5V, VCOM = 0.3V, 3V, VNO = 3V, 0.3V
25 Full
V+ = 4.5V, VCOM = 0.3V, 3V, or VNO = 0.3V, 3V, or Floating
25 Full
V+ = 3.9V, VNO = 3.0V, RL =50, CL = 35pF, (See Figure 1) V+ = 3.9V, VNO = 3.0V, RL =50, CL = 35pF, (See Figure 1) CL = 1.0nF, VG = 2V, RG = 0, (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 3) RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS, (See Figure 3) RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS, (See Figure 5) f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600
25 Full 25 Full 25 25 25 25 25
-
40 50 35 45 192 102 81 -95 0.01
-
ns ns ns ns pC dB dB dB %
Turn-OFF Time, tOFF
Charge Injection, Q OFF Isolation OFF Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion
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Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4), Unless Otherwise Specified (Continued) TEST CONDITIONS f = 1MHz, VNO = VCOM = 0V, (See Figure 6) f = 1MHz, VNO = VCOM = 0V, (See Figure 6) TEMP (C) 25 25 (NOTE 5) MIN TYP 46 233 (NOTE 5) MAX UNITS pF pF
PARAMETER NO OFF Capacitance, COFF COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = +4.5V, VIN = 0V Full 25 Full Positive Supply Current, I+ V+ = +4.5V, VIN = V+ 25 Full Positive Supply Current, I+ V+ = +4.2V, VIN = 2.85V 25 1.65 4.5 0.1 1 0.5 1 12 V A A A A A
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 4.5V, VIN = 0V or V+ Full Full Full 1.6 -0.5 0.5 0.5 V V A
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 2.7V, ICOM = 100mA, VNO = 0V to V+, (See Figure 4) V+ = 2.7V, ICOM = 100mA, VNO = Voltage at max RON, (Note 7) V+ = 2.7V, ICOM = 100mA, VNO = 0V to V+, (Note 6) 25 Full 25 Full 25 Full
0 -
0.55 0.05 0.1 0.9 30 0.8 30
V+ 0.6 0.8 0.07 0.08 0.15 0.15 -
V nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO OFF Leakage Current, INO(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 3.3V, VCOM = 0.3V, 3V, VNO = 3V, 0.3V
25 Full
V+ = 3.3V, VCOM = 0.3V, 3V, or VNO = 0.3V, 3V, or Floating
25 Full
V+ = 2.7V, VNO = 1.5V, RL = 50, CL = 35pF, (See Figure 1) V+ = 2.7V, VNO = 1.5V, RL = 50, CL = 35pF, (See Figure 1) CL = 1.0nF, VG = 1.5V, RG = 0, (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 3) RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS, (See Figure 3) RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS, (See Figure 5)
25 Full 25 Full 25 25 25 25
-
50 60 40 50 115 102 81 -95
-
ns ns ns ns pC dB dB dB
Turn-OFF Time, tOFF
Charge Injection, Q OFF Isolation OFF Isolation Crosstalk (Channel-to-Channel)
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ISL54047
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4), Unless Otherwise Specified (Continued) TEST CONDITIONS f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 f = 1MHz, VNO = VCOM = 0V, (See Figure 6) f = 1MHz, VNO = VCOM = 0V, (See Figure 6) TEMP (C) 25 25 25 (NOTE 5) MIN TYP 0.016 48 236 (NOTE 5) MAX UNITS % pF pF
PARAMETER Total Harmonic Distortion NO Capacitance, COFF COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = +3.6V, VIN = 0V or V+ 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.3V, VIN = 0V or V+ 25 25 Full 1.4 -0.5 0.5 0.5 V V A 0.01 0.52 A A
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 1.65V, ICOM = 100mA, VNO = 0V to V+, (See Figure 4) 25 Full
0 -
1.24 1.34
V+ -
V
DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.65V, VNO = 1.0V, RL =50, CL = 35pF, (See Figure 1) V+ = 1.65V, VNO = 1.0V, RL =50, CL = 35pF, (See Figure 1) CL = 1.0nF, VG = 1V, RG = 0, (See Figure 2) f = 1MHz, VNO = VCOM = 0V, (See Figure 6) f = 1MHz, VNO = VCOM = 0V, (See Figure 6) 25 Full 25 Full 25 25 25 70 80 65 75 53 52 237 ns ns ns ns pC pF pF
Turn-OFF Time, tOFF
Charge Injection, Q NO OFF Capacitance, COFF COM ON Capacitance, CCOM(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 7. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron value, between NO1 and NO2. V+ = 2.0V, VIN = 0V or V+ 25 25 Full 1.0 -0.5 0.4 0.5 V V A
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ISL54047 Test Circuits and Waveforms
V+ V+ LOGIC INPUT 0V tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON VOUT 90% LOGIC INPUT SWITCH INPUT NO COM IN GND RL 50 CL 35pF VOUT 50% tr < 20ns tf < 20ns C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO) -----------------------------R L + R ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
V+
C
RG SWITCH OUTPUT VOUT VOUT VG V+ LOGIC INPUT ON OFF 0V Q = VOUT x CL ON
NO
COM
VOUT
GND
IN
CL LOGIC INPUT
Repeat test for all switches. FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
V+ C SIGNAL GENERATOR V+ C
NO
FIGURE 2B. TEST CIRCUIT
RON = V1/100mA
NO
IN
0V or V+
VNX 100mA V1 IN 0V or V+
ANALYZER RL
COM
GND
COM
GND
Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 3. OFF ISOLATION TEST CIRCUIT
Repeat test for all switches. FIGURE 4. RON TEST CIRCUIT
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ISL54047 Test Circuits and Waveforms (Continued)
V+ C V+ C SIGNAL GENERATOR
NO COM
50
NO
IN1 0V or V+ IMPEDANCE ANALYZER ANALYZER RL
COM NO
IN
0V or V+
N.C.
COM
GND
GND
Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 5. CROSSTALK TEST CIRCUIT
Repeat test for all switches. FIGURE 6. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL54047 is a bidirectional, differential single pole/single throw (SPST) analog switch that offer precise switching capability from a single 1.65V to 4.5V supply with low on-resistance (0.44) and high speed operation (tON = 40ns, tOFF = 35ns). The devices are especially well suited for portable battery powered equipment due to their low operating supply voltage (1.65V), low power consumption (4.5W max) and the tiny TQFN package. The ultra low onresistance and Ron flatness provide very low insertion loss and distortion to applications that require signal reproduction.
V+ OPTIONAL PROTECTION RESISTOR
NO1 N02
C
100 COM1 COM2
IN GND
External V+ Series Resistor
For improved ESD and latch-up immunity Intersil recommends adding a 100 resistor in series with the V+ power supply pin of the ISL54047 IC (see Figure 7). During an over-voltage transient event, such as occurs during system level IEC 61000 ESD testing, substrate currents can be generated in the IC that can trigger parasitic SCR structures to turn ON, creating a low impedance path from the V+ power supply to ground. This will result in a significant amount of current flow in the IC which can potentially create a latch-up state or permanently damage the IC. The external V+ resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many over voltage transient events. Under normal operation the sub-microamp IDD current of the IC produces an insignificant voltage drop across the 100 series resistor resulting in no impact to switch operation or performance.
FIGURE 7. V+ SERIES RESISTOR FOR ENHANCED ESD AND LATCH-UP IMMUNITY
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can be protected by adding a 1k resistor in series with the logic input (see Figure 8). The resistor limits
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the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch. Connecting schottky diodes to the signal pins as shown in Figure 8 will shunt the fault current to the supply or to ground thereby protecting the switch. These schottky diodes must be sized to handle the expected fault current. 2.7V the VIL level is about 0.53V. This is still above the 1.8V CMOS guaranteed low output maximum level of 0.5V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL54047 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example driving the device with 2.85V logic (0V to 2.85V) while operating with a 4.2V supply the device draws only 12A of current (see Figure 16 for VIN = 2.85V).
OPTIONAL SCHOTTKY DIODE V+ OPTIONAL PROTECTION RESISTOR
Frequency Performance
In 50 systems, the ISL54047 has a -3dB bandwidth of 27MHz (see Figure 21). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch's input to its output. Off Isolation is the resistance to this feed through, while Crosstalk indicates the amount of feed through from one switch to another. Figure 22 details the high Off Isolation and Crosstalk rejection provided by this part. At 100kHz, Off Isolation is about 102dB in 50 systems, 118dB into 8, and 124dB into 4, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
INX VNX VCOM
GND OPTIONAL SCHOTTKY DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL54047 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL54047 5.5V maximum supply voltage provides plenty of room for the 10% tolerance of 4.3V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.65V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the Electrical Specification Tables on page 5 and Typical Performance Curves on page 9 for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Logic-Level Thresholds
This switch family are 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.7V to 4.5V (see Figure 18). At
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ISL54047 Typical Performance Curves TA = 25C, Unless Otherwise Specified
0.46 ICOM = 100mA 0.44 0.54 0.52 0.42 0.50 RON (W) 0.40 V+ = 3.9V 0.38 V+ = 4.3V 0.36 0.42 V+ = 4.5V 0.34 0 1 2 VCOM (V) 3 4 5 0.40 0 0.5 1 1.5 2 VCOM (V) 2.5 3 3.5 0.44 V+ = 3.3V RON () 0.48 0.46 V+ = 3V V+ = 2.7V 0.56 ICOM = 100mA
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
1.3 1.2 1.1 1.0 RON () 0.9 0.8 0.7 0.6 0.5 0 0.5 1 VCOM (V) 1.5 2 V+ = 1.8V RON () V+ = 1.65V ICOM = 100mA
FIGURE 10. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
0.55 V+ = 4.3V ICOM = 100mA
0.50 85C 0.45
0.40 25C 0.35
V+ = 2V
0.30 -40C 0.25 0 1 2 VCOM (V) 3 4 5
FIGURE 11. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
0.60 V+ = 3.3V ICOM = 100mA 85C
FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE
0.70 0.65 0.60 85C
V+ = 2.7V ICOM = 100mA
0.55
0.50 RON () RON () 0.55 0.50 0.45 0.35 -40C 0.30 0 0.5 1 1.5 2 2.5 3 3.5 0.40 0.35 -40C 25C
0.45 25C 0.40
0
0.5
1
1.5 VCOM (V)
2
2.5
3
VCOM (V)
FIGURE 13. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 14. ON RESISTANCE vs SWITCH VOLTAGE
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ISL54047 Typical Performance Curves TA = 25C, Unless Otherwise Specified (Continued)
1.1 1.0 0.9 -40C RON () iON (A) 0.8 0.7 0.6 0.5 0 0.4 0 0.5 1 VCOM (V) 1.5 2 1 2 VIN(V) 3 4 5 85C 25C 150 V+ = 1.8V ICOM = 100mA 200 V+ = 4.2V
100
50
FIGURE 15. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 16. SUPPLY CURRENT vs VLOGIC VOLTAGE
1.1 1.0 VINH
800 600 400 V+ = 4.3V 200 Q (pC) 0 -200 -400 -600 -800 -1000 0 1 2 VCOM (V) 3 4 V+ = 1.8V V+ = 3V VINH AND VINL (V)
0.9 0.8 0.7 0.6 0.5 0.4 0.3 1.5 2.0 2.5 3.0 V+ (V) 3.5 4.0 4.5
VINL
FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE
200
FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
200
150 tON (ns) +85C +25C 50 -40C tOFF (ns)
150
100
100
+85C +25C -40C
50
0 1.0
1.5
2.0
2.5 3.0 V+ (V)
3.5
4.0
4.5
0 1.0
1.5
2.0
2.5 3.0 V+ (V)
3.5
4.0
4.5
FIGURE 19. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 20. TURN-OFF TIME vs SUPPLY VOLTAGE
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ISL54047 Typical Performance Curves TA = 25C, Unless Otherwise Specified (Continued)
NORMALIZED GAIN (dB) 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 V+ = 4.3V RL = 50 VIN = 0.2VP-P to 2VP-P 0.01 0.1 1 FREQUENCY (MHz) 10 100 -120 CROSSTALK (dB) GAIN -20 0 V+ = 4.3V RL = 50 0
20
-60
60
-80
ISOLATION
80
-100 CROSSTALK
100
120
-140 1k
10k
100k
1M
10M
140 100M 500M
FREQUENCY (Hz)
FIGURE 21. FREQUENCY RESPONSE
FIGURE 22. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 114 PROCESS: Submicron CMOS
11
FN6503.0 May 31, 2007
OFF ISOLATION (dB)
-40
40
ISL54047 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D A B
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.45 NOMINAL 0.50 0.127 or 0.15 REF 0.15 1.75 1.35 0.20 1.80 1.40 0.40 BSC 0.35 0.45 0.40 0.50 10 2 3 0 12 0.45 0.55 0.25 1.85 1.45 MAX 0.55 0.05 NOTES 5, 9 9 2 3 3 4 Rev. 1 1/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
6 INDEX AREA 2X 2X 0.10 C
N
E
1 0.10 C
2
A A1
TOP VIEW
A3 b
0.10 C 0.05 C SEATING PLANE A1 SIDE VIEW A
C
D E e L L1
(DATUM A) PIN #1 ID L1 NX L 1 2 NX b 5 10X 0.10 M C A B 0.05 M C 5 7 e BOTTOM VIEW (DATUM B)
N Nd Ne
C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) 9L
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 10. JEDEC Reference MO-255.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6503.0 May 31, 2007

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